In reply to Pavel:
The clocking blocks are functioning as they are designed. When S_AXIS_DATA_TREADY changes, the clocking block will wait until the next clock to sample it, hence cb/S_AXIS_TREADY having a 1 clock delay.
In reply to Pavel:
The clocking blocks are functioning as they are designed. When S_AXIS_DATA_TREADY changes, the clocking block will wait until the next clock to sample it, hence cb/S_AXIS_TREADY having a 1 clock delay.