In reply to Pavel:
The issue is with how you connect the interfaces to the DUT.
A clocking block is used inside the interface to ensure that all the signals are sampled properly. However, when you connect the interface to the DUT, you want to connect the top level signals. I didn’t realize you were doing this in your first post.
// module test_int instantiation
test_int test_int_inst (
// Synchro signals and reset
.ACLK (ACLK),
.ARESETN (ARESETN),
// Interface S_AXIS_DATA
.S_AXIS_DATA_TVALID (com_tb_int_in_data_inst.S_AXIS_TVALID),
.S_AXIS_DATA_TREADY (com_tb_int_in_data_inst.S_AXIS_TREADY),
.S_AXIS_DATA_TLAST (com_tb_int_in_data_inst.S_AXIS_TLAST),
.S_AXIS_DATA_TDATA (com_tb_int_in_data_inst.S_AXIS_TDATA),
.S_AXIS_DATA_TUSER (com_tb_int_in_data_inst.S_AXIS_TUSER),
// Interface M_AXIS_DATA
.M_AXIS_DATA_TVALID (com_tb_int_out_inst.M_AXIS_TVALID),
.M_AXIS_DATA_TLAST (com_tb_int_out_inst.M_AXIS_TLAST),
.M_AXIS_DATA_TREADY (com_tb_int_out_inst.M_AXIS_TREADY),
.M_AXIS_DATA_TDATA (com_tb_int_out_inst.M_AXIS_TDATA),
.M_AXIS_DATA_TUSER (com_tb_int_out_inst.M_AXIS_TUSER)
);