Connecting DUT and TB using interface without modports

SystemVerilog
, ,
17

In reply to cgales:

I’m not sure that this is the reason. In testbench I run the task after posedge of ARESETN signal:

    // S_AXIS_DATA
    initial begin
        automatic c_data_buffer #(.TDATA_WIDTH (32), .TUSER_WIDTH (8)) s_data_buffer;
        automatic logic random_valid = 0;

        @ (posedge ARESETN);

        @ (posedge ACLK);

        for (int i = 0; i <= $size(data) - 1; i++) begin
            data[i] = i;
        end

        for (int i = 0; i <= $size(user) - 1; i++) begin
            user[i] = i+1;
        end

        s_data_buffer = new;

        for (int i = 0; i <= $size(user) - 1; i++) begin
            if ( (i > 0 && (i % 10) == 0) || i == ($size(user) - 1) ) begin
                s_data_buffer.push_back(data[i], user[i], 1);
            end else begin
                s_data_buffer.push_back(data[i], user[i], 0);
            end
        end

        com_tb_int_in_data_inst.send_data(s_data_buffer, random_valid);

        ->data_sended_e;

    end