Connecting DUT and TB using interface without modports

SystemVerilog
, ,
14

In reply to Pavel:


while (i <= data_buffer.size() - 1) begin
  if ( (random_tvalid && $urandom_range(1, 0) == 1) || !random_tvalid ) begin
    cb.S_AXIS_TVALID    <= 1'b1;
    cb.S_AXIS_TDATA     <= data_buffer.bus[i].tdata;
    cb.S_AXIS_TUSER     <= data_buffer.bus[i].tuser;
    cb.S_AXIS_TLAST     <= data_buffer.bus[i].tlast;
    @(cb);
    while (!cb.S_AXIS_TREADY) @(cb);
    i++;
  end else begin
    cb.S_AXIS_TVALID <= 1'b0;
    @(cb);
  end
end