Connecting C++ TB with Verilog RTL

Hello,

I have given a project in my HPC class to implement OpenMP in testbenches. For that I need to write a C++ TB. Since this is first try to write a C++ TB I need help to understand that if I am taking a very simple Adder RTL and creating C++ TB then how should i proceed with the same? What tool should I use and what are the things I need to take care of?

In reply to Debasmita Aich:

This is a fairly broad and complex topic. There is no concept of simulation time in C++, so a lot depends on how much timing information your testbench you need to deal with. For example your simple adder has no timing your C++ code could be treated as a function call and all you have to do is compare the outputs of the C++ and RTL. This can easily done using SystemVerilog’s DPI.

But once your C++ code needs synchronization with the timing in the RTL, things get complex quickly. Timing can be synchronized at the physical level, clock cycles, or some other abstract transaction level. Some of this can be achieved with more advanced DPI usage. You can also use SystemC (a C++ library) as a bridge between your C++ code and the RTL. Most simulation tools allow you to instantiate an RTL module inside a SystemC module.

But OpenMP introduces some major challenges as the multi-threading model does not fit at all with RTL simulation threads. The interface into the RTL has to be managed as a single software thread.

You may want to read my DVCon paper that covers some of the issues you may want to know about.