I am a student Researcher who is trying to self study System Verilog Assertions for professional development.
I am trying to implement a simple FIFO and verify it. So I have separate modules for the FIFO design, FIFO test bench, Assertion module and (Interface Module for all the I/O signals (along with Modport)) and a module that will bind the assertion module to the FIFO design module.
My question is, in my assertion module I want to address a signal that is internal to the FIFO design (not an input or output port) to do a certain assertion. Now my interface module does not include this signal as it is not an I/O port. What would be the best recommendation to make the signal internal to the FIFO available to the assertion module through binding.
- Thanks in Advance.