Connect SV interface to VHDL entity using pattern matching

UVM
,
1

Hello,

Can I use “implicit port” connection of sv “interfaces” to vhdl entities?

I want to use the following code to generate a bunch of SV interfaces to a network of devices implemented in VHDL.
genvar i;
for(i=0; i< LARGE_NETWORK_ELEMENTS; i++) begin : dut_inst
Dut_if dut_if();
initial uvm_config_db#(virtual Dut_if)::set(uvm_root::get(),“*”,$sformatf(“dut_if_%0d”,i),dut_if);
end

I would like to use the pattern matching capability of SV (.) so I do not have to map the individual signals but I can’t figure out what to put in the VHDL entity to make it match properly, do both files have to sv for pattern matching to work?
SV CODE
NETWORK_WRAPPER u_network_vhdl_entity( . )

VHDL Entity
entity NETWORK_WRAPPER is
port( what_name_goes_here : in std_logic_vector(G_ADDRESS_SZ-1 downto 0);

2

First of all, it’s not called pattern matching, it’s called wildcard syntax. Connecting between SV and VHDL isn’t something that all tools will support (I know of at least one simulator that doesn’t allow it). Moreover, there could be inconsistencies between implementations (for tools that support it) on how signal names are handled, because SV is case sensitive, but VHDL is not.

In your case, you’ll need to define a top level signal to connect to:


module top;
  logic[g_address_sz - 1:0] some_signal;

  // connect network
  network_wrapper #(g_address_sz) dut(.*);
endmodule

The name of that signal must match with the name defined in the VHDL entity:


entity NETWORK_WRAPPER is
port( some_signal : in std_logic_vector(G_ADDRESS_SZ-1 downto 0) );

Not sure how you drive this signal, but I assume each little dut_if drives a part of this signal, so in your generate block you can connect a part of some_signal to the appropriate interface:


genvar i;
for(i=0; i< LARGE_NETWORK_ELEMENTS; i++) begin : dut_inst
Dut_if dut_if();
initial uvm_config_db#(virtual dut_if)::set(uvm_root::get(),"*",$sformatf("dut_if_%0d",i),dut_if);

// drive part of top signal connected to DUT
some_signal[i+SOME_VALUE:i] <= dut_if.some_interface_signal;
end