I am trying to understand how rand exactly works in system verilog hence I wrote following code :
class A;
//rand bit[2:0] a, b, c;
bit[2:0] a, b, c;
function new();
$display("New of class A");
endfunction
function void display();
$display("class A %0d %0d %0d", a,b,c);
endfunction
endclass
class B;
rand A Ba;
function new();
$display("New of class B");
Ba = new();
endfunction
function void display();
$display("class B %0d %0d %0d", Ba.a,Ba.b,Ba.c);
endfunction
endclass
module top;
initial begin
A a;
B b;
bit check;
a = new();
check = a.randomize();
$display("check = %0d", check);
a.display();
b = new();
assert(b.randomize());
b.display();
end
endmodule
Got output :
New of class A
check = 1
class A 0 0 0
New of class B
New of class A
class B 0 0 0
Output of class makes sense all 0’s.
However I was expecting atleast in class B all variables are randomized.
I think I might have seen B being randomized in UVM testbench.
if i declare variable in class A as rand both A and B objects are randomized.(uncomment the line after class A)
Can someone explain this ?