Confusion regarding with() clause

SystemVerilog
,
1

Hi all ,

A while ago there was a thread related to int’() cast within with() clause ( unable to find it now ) .
It was related to int’() cast inside with() clause of sum().

I tried the following codes ::


 // CODE 1
 class WITH_CLAUSE1() ;

   rand int a , b  ; 
   rand bit [30:0] A[2] ; 
 
   constraint ADDITION  {    
                           A[0] == a ; A[1] == b ;      // [X]
			   a + b == ( 32'd2**32 - 2 ) ; 
		        }   

endclass

With CODE 1 , I see Output :: '{a:'h7FFFFFFF, b:‘h7FFFFFFF, A:’{'h7FFFFFFF, 'h7FFFFFFF}}

With above , MSb of A[0] and A[1] is 0 , since both a and b are Sized to 32-bits with MSb as 0.


 // CODE 2
 class WITH_CLAUSE2() ;

   rand bit [30:0] a[2] ;  
   
     constraint WITH  {    
    			   a.sum() with ( int'( item ) ) == ( 32'd2**32 - 2 ) ;
		      }   

endclass

This has failure on some simulator whereas on some simulator I see both a[0] and a[1] as 'h7FFFFFFF.

Similar to Code1 above , shouldn’t the elements a[0] and a[1] in Code2 both have MSb as 0 ??

Here’s my Question :: [Q1] Is there a difference between Code 1 and Code 2 above ?

2

In reply to Have_A_Doubt:

https://verificationacademy.com/sessions/verilog-basics-for-systemverilog-constrained-random-verification/video/1682?play=1

this is the common question in sv randomization

3

In reply to Have_A_Doubt:

Both a[0] and a[1] should be 32’h7FFFFFFF; that is the only solution for both codes. MSB (bit 30) of a[0] and a[1] are both 1 since they are only 31-bits. You may have run into a tool issue with the reduction operator and this Mentor sponsored public forum is not for discussing tool specific issues. Please contact your tool vendor directly for support to make sure you have the latest version of software installed.