Conflicting constraints

SystemVerilog
, ,
1

Lets say I have a class that has a rand variable like below:

class ABC;
   rand A;

  constraint c_a{
     A == 50;
  }

function post_randomize();
     A = 100;
endfunction

endclass

Is this going to end up in a conflict? I have a conflict even if A was constrained to 100.

2

There is no conflict with the code shown. Only active constraints during randomise() are considered. The constraint solver is done by the time post_randomize() gets called.

3

Thanks Dave.
what if there was a pre_randomize() defined as well as below:

class ABC;
   rand int A;

  constraint c_a{
     A == 50;
  }


function pre_randomize();
     A.rand_mode(0);
endfunction

function post_randomize();
     A = 100;
endfunction

endclass

That should not have any bearing on the randomization of A and also the fact that we are overriding the value in post_randomize? i missed that part of the code earlier. I get a solver issue with the above pre_randomize and none without it.

4

@dave_59 i can confirm that the way i had pre_randomize coded up was causing the solver to fail. i cannot tell why though.

5

All active constraints must be satisfied. Turning rand mode of A off does not deactivate the constraint. You need to turn off the constraint with a_c.constraint_mode(0), or set A = 50;

6

@dave_59 i understand that rand_mode and constraint_mode are exclusive but turning off rand_mode here will set it to default which is 0 and that does not satisfy the constraint. is my understanding correct?

7

I would have used the word independent instead of exclusive. Assuming you have just constructed the class, A would have the default initial value 0 and would not be able to satisfy the active constraint.

8

Thanks @dave_59 that clears my understanding of how it works.
I guess if I had the constraint declared as ‘soft’, that would get rid of the solver failing too.