Hi,
can some one tell me the reason why I’m not able to access the signal in driver. When I’m using config_db set and get in test case and driver respectively
class configknobs extends uvm_componet ;
`uvm_object_utils(test_soft_rst_gear_box_confgknob)
function new(string name = "configknobs ", uvm_component parent=null);
super.new(name, parent);
endfunction : new
constraint bypass_gr_bx_c {bypass_gear_box ==0;}
constraint tx_sync_headr_c {tx_sync_header_i ==0;}
endclass : configknobs
in test case :
class testing extends configknobs;
constraint bypass_gr_box_c {bypass_gear_box ==0;}
constraint tx_sync_header_c {tx_sync_header_i ==0;}
endclass :testing
class normal_test extends uvm_test;
env env_0;
configknobs cfg;
`uvm_component_utils(normal_test)
extern function new(string name=“normal_test”,uvm_component parent=null);
extern function void build_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
endclass : normal_test
function normal_test::new(string name=“normal_test”,uvm_component parent=null);
super.new(name,parent);
endfunction
function void normal_test::build_phase(uvm_phase phase);
super.build_phase(phase);
env_0 = env::type_id::create(“env_0”,this);
cfg = configknobs::type_id::create(“cfg”,this);
factory.set_inst_override_by_name(“testing”,“configknobs”,“");
$display(“before set:”);
uvm_config_db#(configknobs)::set(this,"uvm_test_top”,“cfg”,cfgs);
$display(“after set:”);
endfunction
task normal_test::run_phase(uvm_phase phase);
normal_seq seq;
phase.raise_objection(this);
seq = normal_seq::type_id::create(“seq”,this);
seq.start(env_0.agnt.sqr);
phase.drop_objection(this);
endtask
driver_part:
class driver extends uvm_driver#(sequence_item);
configknobs cfg;
sequence_item item;
uvm_blocking_put_port#(local_trans) driver_put_port;
`uvm_component_utils(driver)
extern function new(string name=“driver”,uvm_component parent=null);
extern virtual function void build_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
endclass:driver
function driver::new(string name=“driver”,uvm_component parent=null);
super.new(name,parent);
endfunction:new
function void driver::build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(get_type_name(),“DRIVER-BUILD_PHASE”,UVM_LOW)
cfg = confgknobs::type_id::create(“cfg”,this);
driver_put_port = new(“driver_put_port”,this);
uvm_config_db#(configknobs)::get(null,“”,“gr_cfg”,gr_cfg);
endfunction : build_phase
task driver::run_phase(uvm_phase phase);
uvm_resource_db#(gear_box_confgknobs)::dump();
$display(“before get :”);
if( uvm_config_db#(gear_box_confgknobs)::get(null,“”,“gr_cfg”,gr_cfg))
$display(“BBBB”);
else $stop;
forever
begin
…
end
endtask:run_phase
out-put observations :
i can able to see the following statements as :
before set: → statement from test case
after set: → statement from test case
before get : ->statement from driver
here im expecting statement as BBBB
instead of that im getting into else part
can any one give me the valuable comments on the above example
-sivajsyamm