Config_db dynamic connection

UVM
,
1

I wanted to make dynamic connection with the desired discrete input/output. In the below line,input SCAN_ENABLE is connected with env[1], with the usage of same line I want to connect this input with env[2],env[3].etc so that I didn’t have to repeat this line again and again.

uvm_config_db #(virtual input_if)::set(null,“uvm_test_top.top_env.env[1]”,“pcm_if_SCAN_ENABLE”,PCM_top.DUT1.pcmif_1_SCAN_ENABLE);

What’s your view on this.
Thanks in advance.

2

In reply to rohitkumar.b:

for(int ii=1;ii<N;ii++)
  uvm_config_db #(virtual input_if)::set(null,$sformatf("uvm_test_top.top_env.env[%0d]",ii),"pcm_if_SCAN_ENABLE",PCM_top.DUT1.pcmif_1_SCAN_ENABLE);
3

In reply to dave_59:
Thanks Dave, I also want to change DUT values with respect to env[*] value, so that connection should be according to the different DUTs.

and how can I set these input/outputs simultaneously for different DUTs before run time.

4

In reply to rohitkumar.b:

I knew that was going to be your next question. SystemVerilog identifiers are not dynamically constructed strings. They must be resolved as you compile the source code. You could create a text macro to help you, but you still would need to repeat the line.

`define config_vif(N) \
uvm_config_db #(virtual input_if)::set(null,`"uvm_test_top.top_env.env[``N``]`","pcm_if_SCAN_ENABLE",PCM_top.DUT1.pcmif_``N``_SCAN_ENABLE);

`config_vif(1)
`config_vif(2)
`config_vif(3)
`config_vif(4)
5

In reply to dave_59:

Can I use this syntax inside a for loop ??

6

In reply to rohitkumar.b:

No. Compiler macros get expanded before parsing any SystemVerilog syntax.
When you put a number in an identifier, you might as well use apple, orange, fig.