Conditional generate block

SystemVerilog
, , , ,
1

Hi ,

I want to implement something similar to this…

if (A == 1)
generate
for (genvar t_gen = 0 ; t_gen <= 158 ; t_gen++)
begin : enc_wl_sel_deck
Assert A;
Assert B;
Assert C;
end
endgenerate
else if (A == 2)
generate
for (genvar t_gen = 0 ; t_gen <= 15 ; t_gen++)
begin : enc_wl_sel_deck
Assert A;
end
endgenerate
generate
for (genvar t_gen = 0 ; t_gen <= 15 ; t_gen++)
begin : enc_wl_sel_deck
Assert B;
Assert C;
end
endgenerate
else
generate
for (genvar t_gen = 12 ; t_gen <= 18 ; t_gen++)
begin : enc_wl_sel_deck
Assert A;
end
endgenerate
generate
for (genvar t_gen = 10 ; t_gen <= 12 ; t_gen++)
begin : enc_wl_sel_deck
Assert B;
end
endgenerate
generate
for (genvar t_gen = 10 ; t_gen <= 12 ; t_gen++)
begin : enc_wl_sel_deck
Assert C;
end
endgenerate

now the issue is the value of A is decided at the runtime, when the simulation runs.
somehow i am not able to implement this format , to which it throws out an error saying null object detected.
can anyone help me to understand the basic implementation of this ?

2

In reply to rtawade:

It would help to know what is in the section that requires a generate block. It’s possible to put concurrent assertions in procedural code and move the conditional statements there.