Conditional assertion inside a module scope

SystemVerilog
, ,
3

In reply to bachan21:

Have you tried using vunit?
vunit is alternative of bind except you don’t need to probe/connect the design signals.
Moreover, you can keep the Assertions and Covergroup out of the design code for readability.
vunit supports the SVA and covergroup to be within and it’s kind of extending the design where you have access to all the design signals.

here is the example I made it for the code you provided.
I added the missing clk and reset signals.
Command to run:
xrun -sv -clean assert_in_mod.sv -propfile_vlog vunit_assert.vunit +ENABLE_ASSERTION

module MyModule (
    input wire shiftData,
    input wire done,
    input clk,
    input reset
);
 
endmodule : MyModule

vunit mod_assert(MyModule) {
    
property shiftData_until_done;
    @(posedge clk) disable iff (!reset & **!$test$plusargs("ENABLE_ASSERTION")**) // Disable during reset
        (shiftData === 0) until (done === 1);
endproperty
 
//if ($test$plusargs("ENABLE_ASSERTION")) begin
  assert property (shiftData_until_done)
  else $display("Assertion failed: shiftData is high before done signal is high");
//end
 
}