Concurrent Assertion :: After ' a ' is True . ' b ' Should Never be True till end of Simulation

SystemVerilog
,
4

In reply to hisingh:
Ran the assertion below. Because there no failure, the error count is zero. At the end of simulation the tool reports the Active count. It canot report the pass action block because the assertion is not finished, and is in the active state.


property  ab ;
  @( posedge  clk )  a  |=>  always !b;
 endproperty   
 ap_always : assert  property (@(posedge clk) a  |=>  s_always[1:10000] !b)  else  $display(" TIME : %0t  AB  FAIL " , $time );
 ac_always : cover  property (ab);