Concerning the "assign" statement

SystemVerilog
5

In reply to dave_59:

In reply to Yasmine4:
There is no such thing a blocking continuous assignment. There are only

  1. procedural blocking assignments
  2. procedural non-blocking assignments
  3. procedural continuous assignments
  4. continuous assignments

Note that you will rarely see (3) used because synthesis tools choose not to support it. They want procedural code to only have on set of sensitivities.

Yes, my mistake again, I meant to say, why is the normal continuous assignment raising an error that disappears when I use the assign keyword?