Concatenation of 2 arrays

SystemVerilog
,
1

I have the following memeber in transaction:

bit [31:0] data [$];

The interface have the following input:

 logic [31:0] WDATA

In the driver I want to assign the concatenation of the transaction data to itself. For examle if the data contain FFFFFFFF, I havt to concatenate FFFFFFFF to FFFFFFFF, and then assign it to the virtual interface

pseudo code:

vif.DATA <= trx.data[i] (concatenation) trx.tata[i]
How can I do it?

2

In reply to saritr:

Hi,

You can concatenate your data as follow:

vif.DATA <= {trx.data[i],trx.data[i]};

Your vif.DATA must be of 64 bits for full data reflection.

3

In reply to saritr:

Either you can use the replication operator.

// Assuming data[i] is 32 it wide vector and WDATA is 64 bit wide vector.
WDATA <= 2{data[i]};

Here is some info about replication operator.

4

In reply to sharvil111:

I did the following:

   int unsigned  j = (vif.WDATA.size())/2; 
   vif.WDATA   <= j{axi_trx.data[i]};   //line 168

I got the following compilation error:

** Error: (vlog-13069) ** while parsing file included at …/sv/gr_ver_pkg

.sv(23)

** at …\sv\axi_bfm.sv(168): near “{”: syntax error, unexpected ‘{’, expecting

‘;’.

5

In reply to saritr:

Forgot to keep a curly brace before replication iterator. Here is a working pseudo code:

module top();
  int j;
  bit [31:0] q[$];
  bit [63:0] data;
  initial begin
    q[0] = 'hABCD_1234;
    j=2;
    data = {j{q[0]}};
    $display("data = 0x%0x",data); // data = 0xabcd1234abcd1234
  end
  
endmodule