Concatenation in `define function in system verilog

SystemVerilog
7

In reply to dave_59:

Hi Dave. Is it possible to concatenate a string with parameter. ANd use that concatenated string as module name in instantiation.

`define func(num) \
	NUMBER_``num

module disp#(
	parameter num = 1
)();
	`func(num) u_mem();          // It should call module NUMBER_1();

endmodule

module NUMBER_1();
   initial $dispay("module called");
endmodule