In reply to Srini @ CVCblr.com:
Rewording my question a bit…
Lets say you have component compA. You build a UVM testbench, and fully verify it.
Now you drop compA into SystemA, again building a UVM testbench. Might someone then disable (or not include) some/all of the verification of compA to speed up performance. After all, compA has already been thoroughly verified in it’s own env. The primary job of the system level environment is to verify system level features, yes?
It may be a stupid question. Anyway, I think what I’ll do is to keep all my checkers (SVA, & scoreboards) and disable coverage on block level environments on a case-by-base basis.