Can any one help me with this compile error? It doesnt seem to be pointing to the original failure. Appreciate ur help.
Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 418: token is ‘interface’
interface bus_if;
^
SystemVerilog keyword ‘interface’ is not expected to be used in this
context.
In reply to dhaval_sanepara:
Strange as the error was pointing on line 418, the actual error is at line 212.
Errors like this are always related to a wrong structure in your code, i.e. a missing ‘;’ or an ‘end’.
In you case it is caused by the following piece of code:
class bus_seq_rw extends uvm_sequence;
`uvm_object_utils(bus_seq_rw)
class bus_seq_rw extends uvm_sequence;
`uvm_object_utils(bus_seq_rw)
rand bit [7:0] data;
The interpretation is a nested class definition, but the corresponding endclass is missing.
To fix remove the 2 lines of code and it will work.