I’ve designed a verification environment using UVM in Synopsys VCS. It worked just fine it compiled and worked. Tried Incisive but it fails during compilation, it cannot import UVM package, it was visible to some files and some files were not. In synopsys VCS it was enough for me to use import:: uvm_pkg in the top module for all other files to have visibility to uvm class libraries. but in Incisive that was not the case.
I solved that issue by importing UVM package at multiple instances (files). I didn’t understand why clearly went to LRM and found this statement:
*"SystemVerilog supports separate compilation using compiled units. The following terms and definitions are
provided:
— compilation unit: A collection of one or more SystemVerilog source files compiled together.
— compilation-unit scope: A scope that is local to the compilation unit. It contains all declarations
that lie outside any other scope.
— $unit: The name used to explicitly access the identifiers in the compilation-unit scope
The contents of files included using one or more `include directives become part of the compilation unit
of the file within which they are included. "*
But it’s not really clear for me, does that mean if I do the following:
"
`ifndef OCPPACKAGE
`define OCPPACKAGE
`include "Config.sv"
`include "Interface.sv"
`include "uvm_macros.svh"
package agent_package;
import uvm_pkg::*;
`include "OutputSequenceItem.sv"
`include "SequenceItem.sv"
`include "Sequence.sv"
`include "Sequencer.sv"
`include "Driver.sv"
`include "InMonitor.sv"
`include "OutMonitor.sv"
`include "Agent.sv"
endpackage // agent_package
`endif
"
Does that mean all files in here have the same compilation unit? and that is why I could not compile it using Incisive ? If I’m importing this agent package to the environment which also coded using UVM I will not be able to compile it unless I do import::uvm_pkg within the environment. Is that what do you mean by separate compilation units?