Comparison of real values

SystemVerilog
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1

Hi,

In the below code, both measured_pclk_period & expected_pclk_period are real types. And at a particular time, both are having same values. Still, the display statement is getting executed as if condition satisfied. I am not sure how simulator entered into if even though greater than operator is used.

My code:
if (measured_pclk_period > expected_pclk_period)
begin
$display(“Pipe clock period %fns does not match expected period of %fns.”, measured_pclk_period, expected_pclk_period);
end

Output:
Pipe clock period 4.000000ns does not match expected period of 4.000000ns.

Please let me know, if this is SV issue or simulator? (I have tried with NC, VCS & MTI for the same. Still all are showing same result)

2

Hi,

In your run, measured_pclk_period > expected_pclk_period might be the actual condition that’s why execution entered in if block.

Increase the precision to see actual values,


$display("Pipe clock period %2.15fns does not match expected period of %2.15fns.", measured_pclk_period, expected_pclk_period);