Comparison between two real variables

SystemVerilog
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1

Hello,

I am facing an issue during comparison between real variables. Timescale is 1ns/1ps. I am measuring the quadrature phase shift between two DDR clocks. The half clock period is configured to 0.667ns. And in comparison I am calculating actual clock phase shift difference using $realtime task (real ddr_clk_diff_real = $realtime - sample_ddr_clk_edge) and getting it 0.334ns. Whereas expected value I am using is 0.667ns/2 = 0.3335. I think because of timescale precision of 1ps the actual value is rounded off to 0.334 from 0.3335. I am using the precision of 0.0000001 in comparison of two real variables. Please share the solution to fix this problem.

Thanks & Regards,
Pinakin

2

There is a general computer science problem comparing real numbers which is magnified by the time precision concept in Verilog. You need to perform your comparisons with a tolerance for rounding errors. See Comparing Floating Point Numbers, 2012 Edition | Random ASCII – tech blog of Bruce Dawson

3

In reply to dave_59:

Thanks Dave for your inputs.

It is working after using the following work around:

longint unsigned clock_period_temp = clock_period_real/2 * 1000; (This will give 334 = (0.667/2) * 1000)
clock_period_real = clock_period_temp / 1000.000; (This will give 0.334)

Best Regards,
Pinakin