Comparing Variable slices of Fixed Arrays

SystemVerilog
, ,
4

In reply to dave_59:

I am mildly confused about this part- item.index>=length_to_compare

Does this limit comparison to length_to_compare (starting from 0) or starts comparison from length_to_compare to the end of the array?

The clause under the with condition, as long as it evaluates to TRUE, the elements are ANDED. Is this statement true. If so, I believe, this would convey the intent more clearly -

array1.and() with (item.index<=length_to_compare ? item == array2[item.index] : 1)

module m;
bit [31:0] array1[100];
bit [31:0] array2[100];
int length_to_compare = 70; // This needs to be able to change

initial
  begin
    foreach(array1[i]) begin
      if (i>length_to_compare) begin
        array1[i] = i+4;
        array2[i] = i+3;
      end
      else begin
        array1[i] = i;
        array2[i] = i;
      end
  end
end

  initial begin
    #2;
    $display("%d", array1.and() with (item.index<=length_to_compare ? item == array2[item.index] : 1));
  end
  
endmodule