Communication Protocol Golden Reference Module Making

SystemVerilog
1

Is it feasible?

For example I built an AMBA AHB protocol between one master and slave? How can I validate that the rules they follow are correct?

2

In reply to haithamx15:

You can read the AHB specification from which you derive SystemVerilog assertions. Those assertions can then reside:

  • Inside the master and slave modules, or
  • In the module that instantiates the master and slave modules, or
  • In a separate bind file.

Once you’ve got your assertions in place then you can either run simulation, in which you need to provide stimulus, or run a formal verification engine that will try and prove that, for the given master and slave, the assertions are true or false.