Common interface(transaction item) for communication throughout the testbench, is this a good style of implementation?

UVM
1

Hi,
I have a testbench which has 4 different kinds of interfaces(2 input and 2 output), so I will be connecting 4 different kinds of agents around my DUT and each agent(input agents only) has a driver,sequencer parameterised with a transaction item which will be used as a communication(TLM ports exports and analysis ports will be parameterized with an item) between driver<–>sequencer and components<–>components in the testbench environment.
My doubt is, do I need to have a common interface such as
“tr_base_item extended from uvm_sequence_item” and
“item_1 extends tr_base_item”
“item_2 extends tr_base_item”
“item_3 extends tr_base_item”
“item_4 extends tr_base_item”
So now I can parameterize all the drivers, sequencers , components and TLMs in my TB with “tr_base_item” and for example when I want to send item_1 from componenent_1 to component_2 I will be doing $cast(tr_base_item,item_1_h) in component_1 and send it to TLM port and when I get it in component_2 I will be doing $cast(item_1_h,tr_base_item) and proceed further.

Is this method good and does it have any advantages or disadvantages with respect to REUSE both HORIZONTALLY and VERTICALLY across the projects??

2

Having them each extended from tr_base_item is a good idea. Each component should upcast the base_item to the particular item it is expecting before operating on it.
However, there is no need to downcast an item_*_h to a tr_base_item before sending it. Since item_1 extends tr_base_item, it IS a tr_base_item, so passing it through a port/export that is expecting a tr_base_item is fine. The only reason you need to upcast on the receiving end

$cast(item_1_h, tr_base_item)

is so that the receiving component can then refer to item_1_h fields.

3

In reply to tfitz:

Hi tfitz,
Thanks for the reply, can you also please share your thoughts on whether this kind of implementation have any advantages or disadvantages with respect to REUSE both HORIZONTALLY and VERTICALLY across the projects??..as I have seen some projects implement particularly in this style.

Thanks,
Neith

4

In reply to UVM Beginner:

Horizontal reuse is usually protocol-specific. If you’re reusing the design IP that these components are intended to verify, then you’ll be able to reuse the verification components as well. You can also reuse the transactions and scoreboard along with perhaps a modified driver that uses the same transaction type but converts it into a different set of pin-wiggles on the bus.
Vertical reuse is also called layering. Please see the Layered Sequences section of the Advanced UVM video course for more details.