Combining sequence in Assertion

In reply to MLearner:
What you are asking is really more of a book, and outside the scope of this forum, which typically provides responses to users being stuck on how to implement an approach, or who are stuck at resolving a particular issue.
There are many presentations and sites that provide information on SVA, a Google search will link you to what you may need.
Again, there are also many books on SVA. Amazon provides free previews of pages of these technical books so that you can see the TOCs and sample pages.
This is really my best recommendations.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115