Combining sequence in Assertion

In reply to ben@SystemVerilog.us:

Hi Ben,
I’m glad that you had time to reply my posts, i follow almost all of your posts, would be happy to see you reply on my queries.
Couls you please give me an example if possible with an waveform or anything similar to it, the problem is i have understood its meaning but have confsion in its usage, so if you could help me out with this then it would be great.
And i will surely consider buying your book for SVA.

Have a great day!!
Cheers!