Combining all reg_models into one

UVM
, , ,
1

Hi

I have three register models generated using ralgen (the third model was not supplied with ralf). Can I combine these register models into one file and instantiate it in TB instead of declaring all three files.

My initial thought is

`include "reg_model1.sv"
`include "reg_model2.sv"
`include "reg_model3.sv"
class uni_rg_model extends uvm_block;
regmodel1 model1; 
//same for 2,3
virtual function build();
  model1.build();
  adding default_map of model 1; 
 repeating for all reg models 

endfunction 
endclass

Can we do this and will we have any issues while accessing registers? Again in env connecting to adapter as I have one apb adapter and all three register models run on apb interface

2

In reply to verific_engi:

How many APB interfacs your DUT has ?

3

In reply to abdelaali_21:

ONE INTERFACE and all sub units work at the same time with common interface .

I will declare a MAP variable and add default maps to it with starting offset of each regmodel as defined in their main blocks. THen will connect to sequencer

4

Declare Mapx variable and add using sub_map all the maps of the reg models in the combined file you are declaring .