Combinationally sampling an input in clocking block

SystemVerilog
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8

In reply to bitfiddler0:

Thanks for the information. I think I have never tried #0 input skew, and misinterpreted the behavior! Also I don’t see any reason to not use #0 skew with RTL.

//Try this,

clocking cb @ (posedge clk);
   default input #1step output #1step
   output wren, data;
   input negedge ready;
endclocking

//Or 
wait(ready); //Without the CB