Hi everyone, I’m looking for a efficient way to instantiate a lot of signals with similar names. For example, I have 20 signals with the name “switch_0”, “switch_1” … “switch_19”. I don’t want to have to replicate the names everytime I need to use it. Can you help me? When I was using Specman E I…

THAT’S what I’m talking about! Works like a charm!!! [WestHamster] Can I generate a number of SystemVerilog properties within a loop? properties, verilog, system-verilog, formal-verification asked by WestHamster on 08:12AM - 17 Oct 12 UTC …

Coding tip: signals with similar name

SystemVerilog

lucaskoelho March 20, 2015, 7:47pm 6

THAT’S what I’m talking about!

Works like a charm!!!

If anyone has something nice to share post here!