Code to check frequency in systemverilog

[Shiv_coder]

Hi,
In a recent interview I was asked to write a code in systemverilog to check frequency.Please if you guys could help me with this that would be great.

Thanks

[user49]

This question was asked many times. I found the following by doing a search at SystemVerilog - Verification Academy

See

How to write assertions for clock frequencies

In reply to Kirankumar V Hiremath: This question was asked many times. You’ll find many results if you use a search. Here is a link to one of them https://verificationacademy.com/forums/systemverilog/checking-clock-period-using-system-verilog-assertion Use realtime and $realtime instead of time and $time. Adjust the period as needed. Ben Cohen http://www.systemverilog.us/ ben@systemverilog.us For training, consulting, services: contact Home - My cvcblr ** SVA Handbook 4th Edition, 2016 …