In reply to trogers:
It looks like you want to be able to use the interface in both a master mode, where ‘signal’ is an output from ‘some_if’, and in a slave/monitor mode where the DUT is driving ‘signal’ into ‘some_if’.
In this case, you need some additional control logic to configure ‘some_if’:
interface some_if (input clk);
wire signal;
bit signal_b;
bit mode=1'b0; // 1 = Master; 0 = Slave
assign signal = (mode==1'b1) ? signal_b : 1'bz;
clocking cb (@posedge clk)
output signal;
endclocking
modport driver (cb);
endinterface
From your driver, change ‘mode’ as appropriate, and set ‘signal_b’ as the output value.