ok, so it’s not really that simple) declaring signal as a “wire” symply forbids any procedural assignments, so it’s not legal to drive signal in any “always” blocks. So, as i see it, if I use clocking block in my testbench, i have to edit my DUT, if it drives signals to the interface with “always” statement, to “assign” driving, right?
Sorry for being so hair-splitting, but it just doesn’t seem to be a right thing, that i might need to change DUT in order to write testbench.