interface in(input bit clk);
logic a;
logic b;
clocking cb@(posedge clk);
output #2 a;
input #10 b;
endclocking
modport TEST (clocking cb);
modport DUT(input a, output b,input clk);
endinterface
module top_1;
bit clk;
initial clk = 0;
always #5 clk = ~clk;
in inter(clk);
dut_1 d1(inter);
testbench_dut_1 t1(inter);
endmodule
module dut_1(in.DUT i1);
always @(posedge i1.clk) begin
i1.b = i1.a;
end
always @(posedge i1.clk ) $display($time, i1.b);
initial begin
#15; $display(i1.b);
end
endmodule
module testbench_dut_1(in.TEST i2);
always @(i2.cb) begin
i2.cb.a <= 0;
end
initial begin
#17;
$display("---------->>>%4d ",$time ,i2.cb.b);
end
endmodule
IN this code . in cloking block i have given input and output skew, my output skew is working well. but input skew is also working similar to output skew.
i.e instead if sampling values before clock posedge, it is getting updated after 10ns of posedge clock .
Why is it happening like that