Clocking Block vs Program Block

SystemVerilog
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Hi All,

According to Chris Spear’s System Verilog for Verification. It’s mentioned that Clocking blocks are used to create the synchronization between DUT and TB signals. In the next section, inside Program block the same statement is mentioned that program blocks are used to avoid race condition between DUT and TB. The basic difference between CB and Programming block is that CB runs in Observed region and PB runs in Reactive. These things I know.

So my question is, can someone tell me the application difference between CB and PB. Also, most of the EDA Vendors’ guidelines say that “Do not use PB”. what is the reason for that.

Thanks,

Mukul

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In reply to mukul1996:

Read this article.

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Hi @cgales ,
The above link is not working, I have confusion regarding this question.
Please help me to know the solution.

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Yes, You are right about the region of executions. The other reasons why we use clocking block over program block is,

  1. Clocking block provides an input and output skews to sample and drive, program block doesn’t.
  2. Clocking block helps in handling clock skew and jitter, program block doesn’t.
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Link is fixed