Clocking block issue

SystemVerilog
,
5

In reply to nnn314:

interface myif (input clk, input Reset);

    //Interface Signals
    logic my_sign;

    // Clocking block
    clocking cb_mst @(posedge clk);
        default input #1step output #1step;
        input my_sign;
    endclocking

    clocking sb_slv @(posedge clk);
        default input #1step output #1step;
        output my_sign;
    endclocking

    //Modports
    modport mon_port(input my_sign);
    modport mst_port(clocking cb_mst);
    modport slv_port(clocking sb_slv);
endinterface

This is just a piece of an highly simplified code. Please remove the clk and reset from MODPORT since those restriction in the access and no changing in the direction (they are always input).