Clocking Block default output skew not applied to output signal in Vivado Simulator 2018.x

[m.sheharyar_00]

clocking cb @(posedge clk);
default output #2ns;

output #3ns read;
output #3ns write;
output #3ns addr;

output data_in;
input  data_out;

endclocking

Expected behavior:

• data_in should inherit the default output skew of #2ns.

Observed behavior in Vivado Simulator 2018.x:

• data_in is driven at the clock edge with no delay.
• If I explicitly write:

output #2ns data_in;

then the delay is applied correctly.

Comparison:

• The same code works as expected on EDA Playground using Synopsys VCS, where data_in inherits the default skew.

Question:

• Is this a known limitation/bug in Vivado Simulator 2018.x, or is there any restriction on the use of default output skew inside clocking blocks?

Attachments:

• Vivado waveform screenshot
• EDA Playground/VCS waveform screenshot
• Minimal reproducible example

[cgales]

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