Clock generator

SystemVerilog
,
1

Could anyone explain the error in this code…
interface clock_if;
bit clk;
class clk_gen;
virtual interface clock_if c;
function new(virtual interface clock_if ic);
c=ic;
endfunction
task gen();
c.clk=0;
forever
begin
#10
c.clk=~c.clk;
end
endtask
endclass
endinterface
module top;
clock_if;
clk_gen clk1;
initial
begin
clk1=new();
fork
clk1.gen;
join_none
end
endmodule

2

What error messages are you getting? Compile error? Run-time error?

You can’t post a section of code and ask what the error is without going into more details.

3

In reply to cgales:

I am getting compile error as, Error: new.sv(23): near “virtual”: syntax error, unexpected virtual and the below is the full code:

interface inter_if;
bit clock;
class test1;
virtual interface inter_if t;
function new(virtual interface inter_if it);
t=it;
endfunction
task run();
t.clock=0;
forever
begin
#10
t.clock=~t.clock;
end
endtask
endclass
endinterface
module top;
inter_if mi();
test aa;
initial
begin
aa=new(virtual interface inter_if mi);
fork
aa.run();
join_none
end
endmodule

4

In reply to gowriashokan:

When you pass an interface to a virtual interface handle parameter, you only pass the instantiation name:


aa=new(mi);

When you fix that error, you will run into several additional errors. The first of which is that the class test1 is contained within the inter_if and is not globally accessible. Why are you trying to create a class within your interface?