Clock generator task - forever statement makes the simulator hang

SystemVerilog
3

In reply to ianmurph:
If you did declare these clock with 4-state logic/reg, you have a race condition that could be eliminated this way:

task clock_gen();
   clk1 = 0;
   clk2 = 0;        
        fork
           
            forever #10 clk1 <= ~clk1;
            forever #10 clk1 <= ~clk2;
        join   
endtask

If that does not fix your hang, you will need to provide more details on how you think your testbench is hanging.