Clock generator task - forever statement makes the simulator hang

SystemVerilog
2

In reply to ianmurph:
There is no reason to declare the clock signals of type logic; declaring them as type bit is sufficient. On
forever #10 clk1 <= ~clk1;
forever #10 clk1 <= ~clk2;
Did you mean forever #10 clk2 <= ~clk2; ??


module top; 
  bit clk1, clk2; 
  logic clk3=0, clk4=0;  // initialized to 0 in the declaration
  initial forever #10 clk1 = !clk1;
  initial forever #10 clk2 = !clk2; // Questioning why 2 clocks of same frequency???
 // If you have clock division use the always_ff
 always_ff @(posedge clk1) clk3  <= !clk3;