Clock generation for bidirectional clock logic

UVM
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1

Hi,

I have to latch a clock in the module top based on the tri-state logic.The reference model/dut has a bidirectional clock.
So, I have introduced a variable called tri-state in my bfm, which becomes “1” during write to dut (using clk_bfm) and which becomes “0” during read from the dut( I want the dut clk).My dut is smbus slave model.

Depending on the tristate , in my top module:

clk = tri_state?1’z:clk_bfm; //clk_bfm is generated in the bfm

I’m not sure how to proceed. Please help?

2

In reply to rudra2255:

I assume you meant you have a continuous assignment to clk in your top module. Then everything you have said so far is correct. I don’t how to help you proceed because I don’t know where you are trying to go with this question. What is your problem?