Clock gating check in SV

SystemVerilog
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1

Hi All,

Just wanted to discuss on how to check whether a clock is running / gated in SV?

Thanks in Advance.

2

It might help to explain using as many words as possible, what your definition of a running or gated clock is. Then we can help you migrate those words into SystemVerilog code.

3

I am trying to clock gate an IP clock and want to check in my test/seq whether it has been successful/not? I dont want to do it by checking the ack/req of the clock but the clock itself.

4

In reply to dave_59:

If i understand correctly what Raj is pointing out is a way to check if clock gets gated after some event.
In general, we use concurrent assertion to check if clock(gated_clk) gets gated when clk_en goes low in which ref_clk is used in assertion. The same is also indicated in this thread,(link)

Dave,
How should a check be implemented for gated_clk in absence of ref_clk. i.e. i just have gated_clk and clk_en and i want to check that my clock(gated_clk) is not gated when clk_en is high and i do not have ref_clk to be used in concurrent assertion.

Thanks