I have tried the below code for checking the clock frequency. This is always pass even if the frequency is not matched. Can anyone please help me by suggesting what necessary corrections are needed? Code: time clock_input= 100ns; property clk_freq; time current_time; @ (posedge clk) disable …

In reply to ben@SystemVerilog.us : 1800 says that The expression on the left-hand side of the inside operator is any singular expression. It looks like the inside does not work on real or realtime types. The use of comparison operators is thus best suited. property p_clk_freq2; real…

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Clock Frequency Checker

SystemVerilog

SagarWakle February 23, 2021, 6:30am 11

Why is '1 required in SV assertion while checking frequency?