Clock delay using case statement

SystemVerilog
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1

Hi,
Can I use in tb the following to create clock delay?

case (a%4)
1: #1;
2: #2;
3: #3;
default: #0;
endcase

This will be implemented inside a clock, and i dont want to create 4 clocks for each case, so i thought of this way, but in simulation nothing happens.

2

In reply to oglick:

It is helpful to post a complete example which demonstrates your issue. The following works fine:


`timescale 1ns/1ns
module case_delay();
  
  initial begin
    for (int a=0; a < 100; a++) begin
      $display("%t: A is %0d", $time, a);
      case (a%4)
        1: #1;
        2: #2;
        3: #3;
        default: #0;
      endcase
    end
  end
endmodule

If you are generating a clock, it is recommended to use a variable delay and change the delay as required:


`timescale 1ns/1ns
module clock_generator();
  
  bit clk;
  shortint clk_delay = 10;
  
  initial begin
    clk = 0;
    forever #clk_delay clk = ~clk;
  end
  
  task update_clk_delay(input shortint new_clk_delay=10);
    @(posedge clk);
    clk_delay = new_clk_delay;
  endtask
  
  initial begin
    #500;
    update_clk_delay(20);
    #500;
    update_clk_delay(50);
    #500;
    update_clk_delay(5);
    #500;
    $finish();
  end
  
  always @(posedge clk) $display("Time is %t", $time);
endmodule