Clock assertions

SystemVerilog
,
1

Hi all, facing a problem while printing the values.

  1. property has local variables “first_change” and period
  2. I am comparing the t_on_period of a clk frequency with the actual clk frequency
  3. when I am trying to display the value of “period” and “t_on_period”, it is printing the values only when the period and t_on_period are equal only, if it’s not equal it is not displaying any values.
  4. I want to know the values when the assertion got failed and passed.

property variables are not accessible outside of the class then how to know the values when assertions got failed.



property TON(clk,clk_period,duty_cycle,enable,reset); 
    realtime first_change; 
    realtime period;
    realtime t_on_period=( ( clk_period * duty_cycle)/100.000 ); 
    disable iff(reset) 
    @(posedge clk)  
     (1,first_change=$realtime) ##0
    @(negedge clk)
      (1,period=($realtime-first_change))##0             
      (period == ton_period,
$display($realtime,"period=%f,t_on_period=%f,first_change=%f,diff=%f",period,t_on_period,first_change,$realtime-first_change));   
  endproperty
2

In reply to Vickyvinayk:

https://verificationacademy.com/forums/systemverilog/there-way-use-sva-propertys-local-variable-value-be-used-outside-property