Class member variable re-declaration

SystemVerilog
, ,
2

Why should it be it simply resides inside of a different namespace and can still be accessed.
Like shown in the following example:


class my_class;  
  bit [7:0] arr [10];  
endclass
 
class my_class2 extends my_class;  
  bit [7:0] arr [15];  

  function ret_super_arr ();
    $display("arr size in super.arr is %0d", $size(super.arr));
  endfunction
endclass
 
module tb;
  my_class  obj;
  my_class2 obj2;
 
  initial begin
    obj  = new();
    obj2 = new();
    $display("arr size in obj  is %0d", $size(obj.arr));
    $display("arr size in obj2 is %0d", $size(obj2.arr));
    obj2.ret_super_arr();
  end
endmodule : tb