Class Member Accessing without Object Creation Possible?

SystemVerilog
,
1

I Compiled the below code, It gave the result with Cadence SImulator, Some One can please me help to understand it, Thanks
CODE:

class p;
    task sum(input int a);
      $display("a is %d",a);
    endtask
 endclass

module test;  
  initial begin
    p p1;
    p1.sum(10);
  end
endmodule

Simulation Result :
irun: 15.20-s038: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
Top level design units:
$unit_0x4ccdf83b
test
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Loading snapshot worklib.test:sv … Done
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
ncsim> source /incisiv/15.20/tools/inca/files/ncsimrc
ncsim> run
a is 10
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
Done

Thanks & Regards,
Ravi Chandra

2

In reply to ravichandrareddyp:

See Why is my code not failing when accessing non static method from not static class? | Verification Academy