Class :final TopPacket extends LinkedPacket;

SystemVerilog
1 
class Packet;
  int addr;

  function display ();
    $display ("[Base] addr= %0d", addr);
  endfunction
endclass

class :final ExtPacket extends Packet;
  int data;

  function display ();
    $display ("[Child] addr= %0d data= %0d", addr, data);
  endfunction

endclass

module tb;
  Packet      bc; 	// bc stands for BaseClass
  ExtPacket   sc; 	// sc stands for SubClass
  
  initial begin
    bc = new ();
    bc.addr = 12;
    bc.display ();
    sc = new();
    sc.data = 11;
    sc.display ();
 end

endmodule

When i ran this code i am getting error , as below

Parsing design file ‘design.sv’
Parsing design file ‘testbench.sv’

Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 12: token is ‘:’
class :final ExtPacket extends Packet;
^

1 error — but from LRM

“The final specifier, preceded by a colon, when applied to classes, specifies that a class shall not be extended:
class :final TopPacket extends LinkedPacket;
…
endclass
class BrokenPacket extends TopPacket; // ILLEGAL: TopPacket specified final!
An attempt to extend a class that was specified as final shall result in an error.” - I am seeing use of final in class. But Synopsys VCS and siemens Questa both throwing error. Pls help on this

2

@dave_59 pls aid me on this

3

I have never seen :final used, and I can’t even think of a case where it would be necessary.

In all likelihood, the simulators aren’t supporting it.

4

This is an enhancement that was added in the 1800-2023 LRM: 07252: Support override hinting (initial/override/final) - Accellera Mantis

Apparently, the open-source simulator Verillator is ahead of the commercial simulators in supporting this feature.

5

Thank you both for the clarification.

I was confused because I was referring to the IEEE 1800-2023 LRM, where class :final is explicitly defined, but both VCS and Questa were reporting a syntax error.

Dave, your clarification that :final is a new 1800-2023 enhancement and that simulator support may still be limited explains the behavior I was seeing.

cgales, I also understand your point that this feature is not commonly seen in practice yet.

I’ll check the specific simulator versions/support and use the 1800-2023 syntax when the tool supports it.

Thanks

Krishna Vedantam

Vedantam@pdx.edu