Checking whether signal is asserted for minimum clock cycles

SystemVerilog
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9

In reply to Srini @ CVCblr.com:

a_min_32_clk_low : assert property (@(posedge clk)
                      !a |-> !a[*32]);

That will work, except that the antecedent needs to be something other than !a since at every clock cycle you’ll have a new attempt with the same requirement (at every clock edge “a” must be repeated 32 more times.
Ben Cohen